<\/p>\n
\u201cIt’s not just an incremental step,\u201d Jay Gambetta, the director of IBM Research, said during a press conference on Tuesday. \u201cIt’s a meaningful leap forward.\u201d Within a decade, Gambetta expects chips with nanostacking to be widely used in data centers, where their improved efficiency could help the facilities better manage their energy consumption.<\/p>\n
\u201cAbsolutely, it\u2019s transformational,\u201d says Dan Hutcheson, vice chair of TechInsights, a technology analysis company. \u201cThis puts another ten, fifteen years on the roadmap.\u201d\u00a0<\/p>\n
Compared to IBM\u2019s previous state-of-the-art architecture, the company reports that chips built with this new approach can do as much as 50% more work in the same amount of time and be up to 70% more energy efficient.\u00a0<\/p>\n
The architecture offers a general way of laying out transistors, and IBM will partner with semiconductor manufacturers to make the actual chips. It anticipates chip designers will deploy the design in many different types of chips, including GPUs and CPUs. \u201cI expect to have many conversations with designers about how they can use this technology,\u201d Huiming Bu, IBM\u2019s vice president of global semiconductor R&D, said in the press conference announcing the new design.\u00a0<\/p>\n
Engineers created IBM\u2019s new chip layer by layer, like a cake. They start by fabricating transistors on one layer of silicon. Then, they place a silicon layer on top of these devices, and they fabricate another layer of transistors directly on top of that. Finally, they create the electrical connections between the two layers of transistors. This kind of vertical stacking, which combines two types of transistors, is known as a complementary field-effect transistor, or CFET, explains Qing Cao, a professor of materials science and engineering at the University of Illinois at Urbana-Champaign, who was not involved with the work.\u00a0<\/p>\n
The company isn\u2019t the only one pursuing this general approach. The biggest chip manufacturers\u2014Intel, Samsung, and TSMC\u2014along with competing research lab Imec in Belgium have been investigating CFETs. IBM says its design is distinguished by the fact that the second layer of transistors do not sit directly on top of the first layer\u2019s transistors; rather, they are staggered, which the company says simplifies wiring, among other advantages.\u00a0<\/p>\n
CFETs like those in IBM\u2019s nanostack architecture contrast with another common approach to making two-tiered chips, such as AMD\u2019s 3D V-Cache and Huawei\u2019s forthcoming LogicFolding technology, Cao says. In those approaches, engineers fabricate the transistors on each layer of the chip independently before bonding the two together. IBM\u2019s new method allows for more precise alignment of the layers, which is important for performance because transistors are so tiny, says Cao.\u00a0<\/p>\n<\/p><\/div>\n
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